STUDY AND DESIGN OF FPGA BASED FULLY CONNECTED NEURAL NETWORKS

Abstract

The project's goal is to design a field programmable gate array (FPGA) based fully connected neural network for handwritten digit recognition. The project involves training the network utilizing the modified national institute of standards and technology dataset (MNIST), as well as designing and simulating a fully linked deep neural network (DNN). Initially, small modules such as memory and activation functions were created independently to test the fundamental functionality of neurons. A multi-layer neural network was created to improve the neural network's overall accuracy by performing the identification of handwritten digits. The network inputs, weights, and outputs are all expressed in this paper using a fixed point representation format. On-chip memory is used to hard-code network weights. Moreover, pipeline registers are utilized to ensure that data flows without error between layers. Using a state machine to control pipeline register access and simultaneously process output from one layer to the next layer with valid output control. Finally, the neural network is assessed using the test bench and MNIST test dataset as inputs, with parameters such as accuracy and resource utilization calculated, which may vary depending on the configuration. The TensorFlow libraries are used for training the network. The whole hardware description of a neural network is written in Verilog. For simulation and implementation, Xilinx Vivado 2020.1 is used in this project.