STUDY OF AMBA PROTOCOL AND VERIFICATION IPs

Abstract

The ARM Advanced Microcontroller Bus Architecture (AMBA) is an open-standard interconnect protocol that connects and manages functional blocks in a system-on-a-chip design. It is easy to build multiprocessor systems with a large number of controllers and components using this bus design. High-performance microprocessors, high-level caches, memory management units, decoders, arbiters, controllers, and other IPs were provided by ARM. However, in order to connect them, an interconnect standard that is simple to design and build for low-power applications is required. The AMBA architecture is the de facto industry standard. Later, the standard was made accessible to the public, allowing others to design and integrate their own IPs. When establishing an interconnection standard, significant design concerns include chip pricing, latency, bandwidth, and the number of IPs that may be linked to the bus. The report presents a detailed study of AMBA APB and AHB protocol and explains its features supported . It also explains about the various signals involved in the protocol . The report also talks about the Intellectual Property and Verification Intellectual property and its importance in today’s modern SOC technology used . In the semiconductor industry, IP (intellectual property) refers to a reusable unit of logic that is licenced to numerous suppliers for use as a building block in various chip designs. It could be logic, functionality, a cell, or even a layout design. More and more functionality is being built into a single chip, resulting in SOC (silicon on chip) designs . Because these IPs are reusable units that may be reused an unlimited number of times once designed, they have become quite popular in the SOC. These IPs may include microprocessors, microcontrollers, and a variety of additional features. JTAG is one of the VIPs which is used in the modern SOCs for verification . It can be used to verify the internal connection of chip as well as the interconnections between the chips when multiple chips are mounted on the board. The report includes the detailed study of JTAG and its register and after studying that the simulation results of bypass and idcode instructions are shown using Verdi tool .