DESIGN AND ANALYSIS OF MODIFIED VOLTAGE BASED SENSE AMPLIFIER FOR LOW POWER APPLICATION

Abstract

In memories and peripheral circuits, the sense amplifier has taken center stage. Longer battery life has become a major challenge for high-speed memories as the need for portable devices grows. In the age of digital technology and VLSI circuitry. SRAM, or static random-access memory, is critical for low-power and high-speed performance. CMOS memory contain sense amplifiers (SA). The saved information is read using SA. Because the sensing amplifier (SA) is a critical component of the read circuitry for both volatile and non-volatile memories, like as FLASH, their performance has a substantial impact on memory performance. The four key performance parameters of SA are access time, energy, power, and area. This thesis describes a sense amplifier with a modified design that includes a dual-voltage dual-tail level restoration voltage latch sense amplifier (DVDTLR-VLSA). The sensing amplifier (SA) is a fundamental component of SRAM and memory systems. In the publications, the voltage mode sense amplifier (VMSA) is found to perform better than the current mode sense amplifier. Many designs have been offered in the literature, each with its own set of benefits. The standard 6T SRAM serves a critical role in cross coupled sense amplifiers. The voltage variations that must be measured are provided by SA. The major classifications of SA have been discussed and compared in this thesis, with the best of the two being explored and explained in sub parts. There have been eight various varieties of VMSA researched, studied, and simulated. All these SAs are differential and cross-coupled SRAM-based SAs. The basic forms of SA structures are the first four differential SAs, while the advanced cross coupled topology of SA is the final four differential SAs. Current, Power, Energy, Transistor Count, and Delay are important SA characteristics that describe the overall performance of SA. On the LT spice simulator, all sense amplifier structures were simulated on the 180 nm technology node and then compared based on parameter and topology. Sense Amplifiers are broadly used in the periphery of Static Random Access Memory (SRAM). Sense amplifiers (SA) are used to fulfills the demand of high speed and low power and act on access time. In this thesis a modified improved Double switch level restoration access transistor sense amplifier (DVDTLR-VLSA) is reported. The design has been simulated in 180 nm technology node with 1.8V operative voltage. The results v of DSLRA-SA are compared with most known sense amplifier topologies based on power, energy, delay, and current parameters in which DVDTLR-VLSA performing admirable. The improved SA is found suitable after examining all the analysis, The design takes a very small amount of power and energy while also improving delay. This thesis excellently finds perfect solution that prove more superior for low power CMOS SRAM. Finally, the performance of DVDTLR-VLSA is superior to that of all other SA topologies. A modified sense amplifier design has been reported based on this assertion, which includes a level restoration circuit (LRC) approach, dual switch (sleep transistors), feedback inverter, and access transistors coupled to bit lines. A modified design is studied and simulated at the 180 nm technology node and compared to current SA in the literature to determine its workability. Propagation delay, power, PDP, and current are the four main parameters that are calculated. The performance of DVDTLR-VLSA is noticeably superior. When compared to a typical cross coupled voltage latch SA (CCVLSA), the enhanced circuit uses half the power. Energy and delay results are also improved. Various analysis such as Dimensional analysis, Temperature analysis and effect of sleep transistors are done for improved SA to examine the performance. A modified cell with sleep transistors has least power, delay and energy and have better.