ANALYSIS OF ASIC DESIGN FLOW BY PERFORMING DESIGN AND VERIFICATION OF ALU BLOCK AND LINT USING SPYGLASS

Abstract

We are living in the era of artificial intelligence where everything which we can imagine is in our hands with the help and emergence of the ongoing technology. There is a need for the semiconductor industries, as well, to make themselves comfortable with the growing pace of the world of technology. With the increase demand of the technologies and the evolution of the products, the big giants of semiconductor industries like Qualcomm, Intel, NXP Semiconductors and Western Digital are finding their way in a best appropriate manner to design the product which is user friendly. There are various constraints which are implemented, which are imposed by these industries like functionality of the electronic device, power dissipation by the product, area occupied and also the reliability of the product. All these constraints, require some special attention and the measurements, which needs to be fulfilled by the design engineers, so that the reputation of the industry, and the competition in the products will be sustained. There are various steps, followed by every Semiconductor industry to make their products the best one. Some of the basic VLSI design flow steps are described in this thesis, and a special focus has been done on the frontend part of the design flow, which includes the designing of the RTL code, and then the Lint process, which generally verifies the syntax and the functionality of the coding so that it can be synthesized properly. And then, verification environment has been created with the help of system Verilog, so that the verification of the RTL code could be done, along with a brief introduction of UPF unified power format is also been studied in this thesis, so that the power aware estimations can be done, along with the functionality checks of the RTL design. The last set of these thesis is a study of the clock domain crossing as clock is one of the crucial nets in the design of complex SOCs, and there are many clock domains running from one part of the SOC to another. So, there must be the proper data transfer between the two clock domains. To understand the basic concept of design and verification of the SOC, the thesis contains one example of ALU, the design part of which is written in the Verilog language, it contains all the proper syntax of the language and the code v | P a g e is synthesizable. And to verify the functionality of this, a new environment is created with the help of system Verilog which includes the concepts of object oriented programming and functional coverage measures. After the verification part of the design process, lint is done to verify the functional checks on the RTL design so that it can be synthesized properly to the gate level netlist.