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Title: | FUNCTIONAL COVERAGE AND ASSERTION BASED VERIFICATION OF COMMUNICATION PROTOCOL USING SYSTEM VERILOG |
Authors: | CHAGANTI, MAHESH SAI |
Keywords: | FUNCTIONAL COVERAGE COMMUNICATION PROTOCOL SYSTEM VERILOG |
Issue Date: | Aug-2021 |
Series/Report no.: | TD-5527; |
Abstract: | There are different types of protocols formulated for specific needs in the Very Large Scale Integrated circuit design. Some of those include On-chip Communication protocols, Interface protocols, Memory management protocols, I/O protocols. A protocol helps devices connect to each other and acts a mediator which carries data, addresses and other information required for the communication. There are different types of protocols which define a set of rules for the communication to happen. Each protocol is uniquely defined for the needs. Generally a protocol needs to be functionally verified in the design stage itself. Suppose at a later stage a bug is encountered it takes huge amount of money, time and work to be put in to fix that. Hence it is recommended to fix any errors or bugs in the early stages. These days Verification engineers are at high demand for this reason. Generally for a design with more complexity, the verification environment is developed using System Verilog. As the title of project suggests, the Functional Verification and Assertion based verification is performed for a communication protocol using System Verilog. The project aims on creating a testbench environment using the most common Hardware Verification Language(HVL). The design involves an interfacing block which can be employed in between an APB Master and an SPI Slave. So it acts fairly as both APB slave and SPI Master. Advanced peripheral bus(APB) is a low power peripheral protocol under Advanced Microcontroller Bus Architecture(AMBA) bus. AMBA is an enrolled brand name of ARM Ltd. Serial Peripheral Interface(SPI) is a full duplex serial communication protocol developed by Motorola. APB is in a way considered to be a parallel bus. It is capable of upto 32 bit wide data transfer between the master and the slave. x In the project, the focus is on the Design of the APB slave Deisgn of SPI Master Creating a verification environment to verify if the read and write operations are done successfully without any mismatches. Since AMBA is a very vast protocol and has many components like AHB, AXI. The APB bridge here acts as a communication bridge between the AXI and the APB bus. Here the APB bus is designed to communicate with the peripherals. AMBA is generally considered as the basic interconnect specification. Since it has the bus architecture, it enables the assembly and organization of the functional blocks in an SoC design. AMBA helps in even multiprocessor designs where many components and peripherals are involved. These days, every other ASIC or SoC is in a way incorporating AMBA bus architecture. On a variety of processors, which are a part of cellphones and gadgets use AMBA protocol. So, APB interface is picked up as an input. One of the most used serial communication protocols is Serial Peripheral Interface. It is used for communication with the external peripherals serially. It acts as one of the high speed and highly reliable seral data stream supporting protocol. So the design this work emphasises, is about connecting these two protocols. The input comes from an SoC device which employs a high end communication and the output obtained will be a serial data stream driving a peripheral device like a Flash memory or a display driver. |
URI: | http://dspace.dtu.ac.in:8080/jspui/handle/repository/18946 |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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Mahesh_Sai_Chaganti_Thesis_M.TECH.pdf | 2.08 MB | Adobe PDF | View/Open |
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