ANALYTICAL MODELING AND SIMULATION OF DOUBLE GATE TFET FOR LOW POWER DESIGN AND PERFORMANCE ANALYSIS OF CNWFET

Abstract

With the semiconductor industry scaling down to the nanoscale regime, the three factors come hand in hand that are namely the speed, power and the area. These three factors are inter-relatable and furthermore the power is classified as power consumed and the power dissipated. As we reduce the size of the Integrated Circuits (ICs), the power consumed by the circuit should also be reduced, and at the same time some effects become prominent at the nanoscale and therefore need to be considered. At the nanoscale, as these effects became prominent, this led to the modification in the structure of the devices to be used for the low power applications. Moore’s law has been the backbone of the VLSI industry which says that the transistors on the chip doubles every eighteen months and this has been followed up till now. The designing of the devices and the circuits on the EDA tools provided by the industry reduces the cost of manufacturing by a large scale as the fabrication of the devices is costly process. This work proposes about the modelling of the TFET (Tunnel Field Effect Transistor) device that finds out the surface potential of device using the mathematical models. The work has been carried out using the TCAD Tools (Technology Computer Aided Design). This device proposes a good ON current for a device to operate and also the lower subthreshold swing than that of the conventional MOSFET device. The work done here is based on a 2D model of the Poisson’s equation that is solved using the Parabolic approximation method and also certain conditions that limit the boundaries of the device called the boundary condition for a device and the conditions differ from region to region of the TFET device. Finally, the results have been simulated and compared with the previously work done on the Analytical modelling of the TFET device for a nanoscale regime.