Please use this identifier to cite or link to this item: http://dspace.dtu.ac.in:8080/jspui/handle/repository/18938
Full metadata record
DC FieldValueLanguage
dc.contributor.authorCHAUHAN, DEEPAK-
dc.date.accessioned2022-02-21T08:48:44Z-
dc.date.available2022-02-21T08:48:44Z-
dc.date.issued2021-08-
dc.identifier.urihttp://dspace.dtu.ac.in:8080/jspui/handle/repository/18938-
dc.description.abstractThe ARM Advanced Microcontroller Bus Architecture (AMBA) is an open-standard interconnect protocol for connecting and managing functional blocks in a system on a chip design. With this bus architecture, it is easier to construct multiprocessor architectures with a high number of controllers and components. ARM gave various IPs such as, high performance microprocessor, high level cache, memory management unit, decoders, arbiters, controllers, etc. But to connect them, there needs to be an interconnect standard which is easy to design and built for low power applications. This de facto standard is known as the AMBA architecture. Later, the standard was made open for others to build and integrate with their own IPs. On chip price, latency, bandwidth, and number of IPs can be connected to the bus are taken as key design considerations while developing an interconnection standard. For our work, target device used for obtaining synthesis results is ZYNQ-7000 FPGA, which is increasingly becoming popular among the FPGA engineers due to its advanced features that make it stand out among all the boards in the presence of an ARM cortex A9 chip which is the main reason for its usage as a system on chip (SoC). Having an integrated support for PCI Express also helps it to persuade its dominance over other FPGAs known to us. For simulations and synthesis, XILINX VIVADO 2019.2 tool has been used. The implemented designs have been analysed in terms of hardware utilization (number of slices, which is comprised of Look Up Tables and Registers), timing (delay in ns) and power consumption (in Watts).en_US
dc.language.isoenen_US
dc.relation.ispartofseriesTD-5519;-
dc.subjectFPGAen_US
dc.subjectBUS PROTOCOLSen_US
dc.subjectAMBAen_US
dc.titleSTUDY AND FPGA BASED DESIGN OF BUS PROTOCOLSen_US
dc.typeThesisen_US
Appears in Collections:M.E./M.Tech. Electronics & Communication Engineering

Files in This Item:
File Description SizeFormat 
Thesis_Deepak_Mtech_VLSI_05 (1).pdf3.26 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.