DESIGN OF PARITY PRESERVING REVERSIBLE LOGIC CIRCUIT FOR LOW POWER APPLICATIONS

Abstract

Arithmetic and Logical Unit (ALU) and Adders are key aspects of the digital world and requires colossal amount of power. This report outlines a new design of one-bit Parity Preserving Reversible ALU circuit, 8-bit Kogge Stone adder and 16-bit Brent Kung adder. To design these circuits with low power dissipation, we have used the concept of Reversible Logic computation. Conventional Circuits dissipate an enormous amount of power due to the loss of information bits in computation, but Reversible Circuits has no data loss as one on one mapping between outputs and inputs which leads to the minimization of power dissipation. In our design, we have used Parity Preserving Reversible Gates which are having Fault tolerance property as fault occurring at internal nodes results in an error at the output. So, Parity Preserving Reversible Gates is the one in which Output Parity remains same as of the Inputs. The aimed circuits have been carried out using Xilinx ISE 14.7 version software in Verilog HDL. To demonstrate the efficiency of proposed circuits, each subpart is shown in terms of various parameters such as Quantum cost, Ancilla Inputs, Gate Count and Garbage Outputs and also a comparison with existing work is shown. The intended design is far better than the existing one because of its fault-tolerant capabilities. So yet, no Kogge Stone adder and Brent-Kung adder circuit employing Reversible Logic Gates with Fault-Tolerant capabilities has been suggested, to the best of our knowledge. The proposed circuits extend its application over DNA mapping, Optical computation, cryptography, nanotechnology, quantum computing and digital signal processing.