STUDY OF GaN-BUFFERED TRENCH GATE MOSFET

Abstract

This Project presents T-CAD simulation of GaN-buffered trench gate MOSFET (GaN-BTG MOSFET). We investigated the numerical simulations on GaN-BTG MOSFET for the suppression of SCEs and the effect of the high-k buffer on the linearity/analog performance and Low-power applications. Different electrical characteristics and linearity/analog parameters; drain current (Id), transconductance (gm), higher order transconductances (gm2, gm3) O/P conductance (gd), transconductance generation factor (TGF), 2 nd and 3 rd order of Voltage Intercept point, 3 rd order

of Current Intercept Point, 1-dB Compression Point, 3rd

-order Intermodulation Point, 2nd and 3 rd

orders of Harmonic Distortion Point have been analyzed. From the simulated results obtained, we have found that the use of elevated-k buffer remarkably improves the electrical as well as analog figure of merits (FOMs) of the device while linearity parameters for Low-power applications needs more investigation. Thus, the GaN-BUFFERED TRENCH GATE MOSFET can be considered as suitable candidate in digital and analog Ckt. applications. Results recommend that the introduction of GaN instead of silicon in a trenched gate structure not just improves the device’s performance at room temperature (300K) yet additionally enhances the thermal stability of the device. The simulations are observed and are supported by the data presented in the results section which are being performed using TCAD tool ATLAS and Deckbuild.