DESIGN OF ENERGY EFFICIENT TRANSCEIVER BLOCKS FOR WIRELESS SENSOR NODES

Abstract

Sensor networks have been recognised as one of the most advanced technologies of the 21st century with vast practical applications. The life of a sensor network is mainly determined by its energy consumption. Commercially available sensor nodes are battery driven devices. As most sensor nodes are deployed widely scattered and in isolated areas, replacing battery is not an option. This dissertation focuses on extending the lifespan of sensor networks by reducing energy consumption in design and operation of sensor nodes. The study goes in depth to analyse the state of art technology to achieve energy efficiency in sensor nodes and identify scope for further research in this field. In the architecture of sensor nodes, multipliers are the main blocks for designing an energy efficient processor. Vedic Mathematics provides principles of high speed multiplication. The main reason for power dissipation in multiplier circuit is due to power dissipation of full adder circuit. Low power multipliers have been designed by using low power adders. Motivated by this, a high speed Vedic multiplier has been designed using multiplexer based adder. When compared with existing Vedic multipliers, proposed designs showed significant improvement in reduction of delay and energy consumption. Sensor nodes consume maximum power during data communication. So processing data locally at each node in a sensor network is important for minimizing power consumption. High processing speed and low area designs are in ever growing demand. In order to predict outcomes, based on previous inputs, ALU can be designed with neurons. Processing speed of ALU can be improved by replacing conventional multipliers with Vedic multipliers. This research work suggests implementation of high speed ALU using Vedic neurons. The analysis of the results shows that the proposed design leads to x reduction in the delay and reduction in LUT count (an indicator of area) of the ALU. Use of energy efficient power amplifiers is an essential requirement for sensor nodes, as power amplifiers are responsible for the main power consumption in the transceivers of sensor nodes. Again, wider band width is another important requirement for power amplifiers used in sensor transceivers especially in wireless visual sensor networks and wireless multimedia sensor networks. Reliability of a power amplifier can be increased by designing it at smaller supply voltage. This thesis suggests improvements in design of power amplifier in class E configuration, for transceivers in wireless sensor nodes. In order to achieve wider band width, cascade of common drain followed by common source in class E configuration has been designed; and for more reliable operation with higher efficiency, class E in double cascoded has been implemented. The proposed designs, when simulated in SPICE, higher efficiencies and band widths have been achieved. This research also explored to design a robust solar energy harvesting system to enhance life time of sensor nodes. Proposed solar energy supply system mainly consists of a solar panel, rechargeable battery and a control circuit. To obtain sufficient voltage to charge battery, electrical energy generated through panel is boosted by boost converter. Different sensor nodes are supplied with energy from this system. An inverter is also designed for AC applications. Experimental results show that this compact, self-sufficient system enables outdoor based wireless sensor network nodes to operate successfully for longer periods.