REALIZATION OF TREE MULTIPLIERS AND THEIR PERFORMANCE EVALUATION

Abstract

Multipliers are the most vital part of any computational applications for real time data processing systems. Hence designers tries to make an efficient multiplier design on the basis of trade-off between the design constraints i.e. speed, power and area. In this project we realize tree multipliers (Wallace Tree and Dadda multiplier) and evaluate their performance using Verilog in Vivado by selecting Zynq-7000 xc7z014sclg484-1 FPGA. The Tree multiplier architectures are designed in three stages which are, partial product generation, their reduction and the final addition stages. Here in partial product reduction stage, for the reduction of partial products, m:n compressors are used. For the final addition stage different adder designs are used. The main objective of this work is to implement different designs of adders and use them in Tree multiplier to investigate the better design between Wallace tree and Dadda multiplier. After that 4:2 compressor are used in reduction stage and implement different designs by using this reduction stage. A new design of tree multiplier is proposed and compare with other existing designs.