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dc.contributor.authorDAHIYA, ISHA-
dc.date.accessioned2021-07-19T09:08:34Z-
dc.date.available2021-07-19T09:08:34Z-
dc.date.issued2021-05-
dc.identifier.urihttp://dspace.dtu.ac.in:8080/jspui/handle/repository/18375-
dc.description.abstractIn this work, the analog performance for Ferroelectric-Dual Material Oxide Stack-Double Gate FET (Fe-DMOS-DG FET) has been assessed and its effectiveness in reducing short channel effects (SCEs) has been analyzed. The derived parameters and results have been analysed in comparison with the conventional bulk MOSFET having same channel length. We are using gate metal comprising of two different materials to have better control over the channel. To reduce the injection of hot carriers, in one case we have used a ferroelectric layer on a thin SiO2 interface layer, and in another case, we have used a ferroelectric layer on an oxide stack consisting of high k-dielectric and SiO2 as gate insulator material. Parameters like ON current, OFF current, Id vs. Vg plot, Transconductance vs. Vg plot, threshold voltage, and value of sub-threshold slope are considered. It has been concluded that the new device has less subthreshold current, resulting in a lower subthreshold slope when compared to bulk MOSFET. Also, the electric field and carrier concentration along the channel are investigated, and it has been found that the novel device enhances carrier transport in the channel. The silvaco ATLAS device simulation software is used to do the numerical calculations in order to validate the results.en_US
dc.language.isoenen_US
dc.publisherDELHI TECHNOLOGICAL UNIVERSITYen_US
dc.relation.ispartofseriesTD -5184;-
dc.subjectCOMPUTER AIDED DESIGNen_US
dc.subjectFERROELECTRIC-DUALen_US
dc.subjectSTACK- DOUBLEen_US
dc.subjectMOSFETen_US
dc.titleTECHNOLOGICAL COMPUTER AIDED DESIGN AND SIMULATION OF NOVEL FERROELECTRIC-DUAL MATERIAL OXIDE STACK-DOUBLE GATE FETen_US
dc.typeThesisen_US
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