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DC Field | Value | Language |
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dc.contributor.author | SINGH, NISHU | - |
dc.date.accessioned | 2021-03-31T06:58:53Z | - |
dc.date.available | 2021-03-31T06:58:53Z | - |
dc.date.issued | 2020-08 | - |
dc.identifier.uri | http://dspace.dtu.ac.in:8080/jspui/handle/repository/18284 | - |
dc.description.abstract | This paper presents detailed design of n-channel FinFET and n-channel GAAFET with physical gate length of 28 nm using COGENDA Visual TCAD. For the designed device silicon is used as dopant, silicon oxide as spacer and aluminium as metal contact in both the devices. The work functions for the n-channel and p-channel GAAFET is set as 4.5 eV and 4.97 eV respectively, and same for n-channel and p-channel FinFET. The electrical characteristics of the devices like ON current (ION), leakage current (IOFF), sub-threshold swing (SS), drain induced barrier leakage (DIBL) are extracted through simulations for both the devices. Further, to check the device functionality in circuit applications two digital application of each devices namely an inverter and a NAND GATE are designed. A comparative study of various performance parameters like noise margin, propagation delay and power consumption has been done between the proposed GAAFET and dual gate FinFET (DG FinFET) based applications, which establishes the performance improvement in GAAFET based designs. | en_US |
dc.language.iso | en | en_US |
dc.relation.ispartofseries | TD-5059; | - |
dc.subject | FINFET | en_US |
dc.subject | GAAFET | en_US |
dc.subject | NANOSCALE | en_US |
dc.title | FINFET AND GAAFET FABRICATION IN NANOSCALE AND ITS APPLICATIONS | en_US |
dc.type | Thesis | en_US |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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M.TECH. NISHU SINGH.pdf | 2.01 MB | Adobe PDF | View/Open |
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