COMPARISON OF VARIOUS ADDER IMPLEMENTATIONS ON CMOS 90nm TECHNOLOGY USING CADENCE VIRTUOSO AND LTspice

Abstract

Adders form an almost imperative component of every contemporary integrated circuit. Since mobile industry is rapidly growing thus speed, area and power efficient arithmetic units are required to satisfy the market needs. The prerequisite of the adder is that it is predominantly fast and secondarily efficient in chip area. Several types of adders are available in practice; each type is used for meticulous purpose based on their performance and features. In this paper, the multiplexer based full adder is implemented in the design of various adders. These adders are compared on the basis of their execution parameters i.e. delay and power distribution by using conventional full adder, Gate level design full adder and a multiplexer based full adder. Adders play a key role in arithmetical operations and used in computational devices. We have proposed a design of four different adders, which relatively requires power and delay. Additionally the proposed design is more efficient in power dissipation. Even though a full adder is being designed with efficient power dissipation but there is always the scope of improvement in terms of reduction in power dissipation. To overcome this issue we have designed different adders and compare the power dissipation of different adders and reached to optimum solution from the alternatives. we have compared various limits for the proposed and existing mechanisms using different tools.