CURRENT MODE LOGIC WITH ENHANCED PERFORMANCE

Abstract

The recent advancement in VLSI technology has facilitated the integration of digital and analog circuits on a single chip. This integration has enabled the user to directly take the data from the real world and process it within a digital system. A single chip realization results in improved performance, lower cost and smaller size. It, however, poses critical constraint due to the switching noise in CMOS digital circuits which gets coupled to the analog parts and degrades their accuracy. This problem becomes severe at higher operating frequencies as aggressive technology scaling is often used to improve the chip performance and the integration levels. Therefore noise becomes important along with design matrices such as area, power consumption and speed; and needs attention. To minimize the effect of noise, research efforts are directed towards (i) minimizing noise coupling (ii) reduction of switching noise generated in CMOS digital circuits. Several techniques are suggested at different levels of abstraction which fundamentally work on limiting the coupling of the noise to analog parts. Emergence of various low noise logic styles is the outcome of the considerable progress in the direction of reducing switching noise generation which is achieved by keeping power supply current nearly constant during the switching event and/or working with smaller voltage swings. These logic styles can be classified in four categories namely current balance logic (CBL) style, current steering logic (CSL) style, folded source-coupled logic (FSCL) style and the MOS current mode logic style. MOS current mode logic (CML) style among these is attractive as it addresses both the issues and is explored in this work. The work on CML gates ranges from modifying the basic topology, analysis and design, to the applications in communication systems (phase-locked loop and ring vi

oscillators), optical fiber links (multiplexing and demultiplexing) and microprocessors and signal processors, (adders, multipliers and compressors). The prime concern of these is to provide better performance and enable designer to adopt systematic design methodology. A CML gate primarily consists of a pull down network (PDN) to implement the logic function, a current source that maintain a constant bias current, and a load to perform the current to voltage conversion. New topologies are developed in this work for reducing the minimum power supply voltage requirement, eliminating the use of CMOS circuit elements, decreasing power consumption, enhancing speed, reducing the gate count in circuit realization. These are achieved by applying modifications in the PDN, load, and the current source sections of the basic CML gate. The proposed topologies are analyzed and suitable design procedure is put forward. The power supply requirement in a CML gate is decided by the number of source coupled transistor pair levels in the PDN and can be lowered by reducing this number. The triple-tail cell concept is introduced in the PDN and new topologies are developed. An analytical approach to model their behavior is presented. An important contribution in this topic is the identification of the design cases where the proposed topologies can be advantageously adopted. The static power consumption of a CML gates is a major hindrance in employing these for portable system design. In this research work, the scheme employing dynamic current source is considered. New improved dynamic CML (D-CML) gates are examined and the techniques to implement multi-stage applications are also discussed. The elimination of the CMOS inverter from the available dynamic current source and a new self-timed buffer are the major contributions in this area. vii

The speed of the CML gates needs to be improved in order to meet the high data transmission rate. A new active load without using any passive component is presented. New differential and PFSCL topologies are developed and are examined. A complete mathematical model for the static parameters and the delay is developed and a design procedure is put forward. The improvement in the speed of the CML gates through the capacitive coupling phenomenon in the proposed load is the main contribution. The conventional NOR based realization of PFSCL circuits consist of multiple gates. An alternate approach that reduces the gates count in PFSCL circuit realization is proposed wherein triple-tail cell concept is applied. The development of a new fundamental cell and its various configurations is the research contribution. Tri-state circuits find ubiquitous use in Field Programmable Gate Arrays (FPGAs), microprocessors and clock/data recovery systems. Two CML tri-state circuits are available in literature. In an effort to the lower power consumption, a new CML tri-state circuit is proposed. All the theoretical propositions are verified through extensive SPICE simulations using TSMC 0.18 µm technology parameters and are compared with the existing counterparts to demonstrate their effectiveness.