REALIZATION OF PULSE TRIGGERED D FLIP FLOP

Abstract

The evolution of hand held devices and desire to place increased functionality on single chip has led to increased power consumption. This has necessitated to explore methods to lower overall power consumption. Flip flops are the fundamental storage element and are used for sequential circuit design, the power consumption in these elements need be reduced. The pulse triggered (PT) flip flop are addressed in this work as it has lower power consumption in comparison to master slave flip flop. The PT flip flops are classified as–implicit and explicit. The explicit pulse triggered D flip flop consists of a latch circuitry a pulse generator circuitry which can be reused in different flip flops. The implicit type flip flop, on the other hand, requires separate pulse generator circuitry for every flip flop. So it consumes more power than explicit type. In this project new topologies of explicit pulse triggered D flip flop are presented which use available four transistors based pulse generator and/ or modified the latch circuitry. The PT flip flops are simulated using CMOS 90nm process technology at 1V supply voltage using Cadence Virtuoso. Simulation results shows that the proposed topologies consume less power in comparison to the other PT flip flops and also shows improvement in delay.