LOW POWER MULTI-VALUED ARITHMETIC LOGICAL UNIT DESIGN USING CNFETS

Abstract

Binary logic and MOS devices have been in use since inception of the design era, but now due to advancement in VLSI industry binary logic has become tedious and complicated. To overcome this challenge Multi-valued logic (MVL) such as ternary and Quaternary Logic (QTL) can be used .MVL designs has an advantage over binary logic deigns with respect to area and interconnects complexity. In this report, we present the design and performance of QTL Full Adder (QFA), Quaternary Multiplier (QM) and QTL Arithmetic and Logical Unit (QTL ALU) using CNFET. For design purpose we have used the Stanford Virtual-Source Carbon Nanotube Field Effect Transistor Model version 1.01 with sub 10nm CNFET technology. The design tool used for simulation is Cadence Virtuoso. This work presents novel multiplexer based approach to design QFA, QM and QTL ALU using CNFET. The proposed QTL ALU design has been compared against the existing CNFET based QTL designs and it is found that proposed ALU design is 90–99% better in terms of power, delay, PDP and EDP.