STUDY OF PHYSICAL DESIGN FLOW, CHALLENGES AND ITS SOLUTIONS

Abstract

Physical design is all about placing instances defined in the netlist and connecting them by routing through metal layer stack to satisfy design specifications such as performance, power and area (PPA). Current IC designs have multi million instances that are interconnected with several stack of metal layers that connect these instances. Manually performing each step in the design process is not feasible, takes huge amount of time and is error prone. The complexity in designing a multi-million instance based IC is huge and hence we need dedicated automation flows that complete specific tasks needed to be performed at each step in the design which reduces design time and errors. These flows require knowledge and understanding of EDA tools and scripting languages such as Tcl, Perl or Python. In addition to complexity, as time to market for chips is decreasing, reuse of IP (Intellectual Property) blocks is highly preferred in each design. Inputs to physical design are the most important files that you will need to start your design process. If the inputs are read in the EDA tools without any issues (warnings and errors), then your physical design flow goes smooth. In today’s IC design, because of huge design complexity, hierarchical design approach is followed. What this means is, the entire chip is divided into partitions or blocks that are interconnected at a top level module. v

Physical Design is all about optimization. Thus, floorplanning is a highly iterative process which takes into account the hard blocks and soft blocks used, memories, IO pads and their placement in the design, routing possibilities between different blocks and inside the blocks, power grid structure for each macro and cell in the design, and also the aspect ratio and IO structure of the entire design.