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DC Field | Value | Language |
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dc.contributor.author | JAIN, POOJA | - |
dc.date.accessioned | 2019-10-24T04:50:58Z | - |
dc.date.available | 2019-10-24T04:50:58Z | - |
dc.date.issued | 2019-07 | - |
dc.identifier.uri | http://dspace.dtu.ac.in:8080/jspui/handle/repository/16712 | - |
dc.description.abstract | A new advanced strategy has been proposed and actualized to detect and remove DAC noise used in the feedback loop of Delta Sigma ADC comprising multi-bit quantizer. The technique has been intended for fast and high-resolution systems where the mismatch error shaping becomes incapable. The system has following highlights: First, it does not require any additional analog hardware. Second, the technique keeps running in the background and Third, the technique works under exceptionally low Oversampling Ratios (OSRs). The procedure can possibly enhance the ADC output by improving the Signal to Noise Distortion Ratio excessively near that of the perfect case. The strategy demonstrates its adequacy in evacuating the DAC noise and enhancing the resolving power of the test ADC under small OSRs. The presentation of the proposed method has been confirmed with MATLAB reproductions. | en_US |
dc.language.iso | en | en_US |
dc.relation.ispartofseries | TD-4559; | - |
dc.subject | DIGITAL TECHNIQUE | en_US |
dc.subject | DAC ERROR | en_US |
dc.subject | DELTA SIGMA ADC | en_US |
dc.title | A FULLY DIGITAL TECHNIQUE FOR THE ESTIMATION AND CORRECTION OF DAC ERROR IN MULTI-BIT DELTA SIGMA ADC | en_US |
dc.type | Thesis | en_US |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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2k17_vls_16_ pooja_jain.pdf | 2.61 MB | Adobe PDF | View/Open |
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