NEW REVERSE CARRY PROPAGATE ADDER USING MODIFIED GDI TECHNIQUE

Abstract

Addition is the most important function in arithmetic and logical operations. Approximate Computing can be used to reduce the number of transistors, delay and power constraints in VLSI design, which makes the use of approximate adders possible in error-tolerant applications. Existing Approximate Reverse Carry Propagate Adder designs [1] have proved to be advantageous in improving these constraints. A new design of Reverse Carry Propagate Adder has been proposed using Modified-Gate Diffusion Input (GDI) technique [7]. A 4-bit Multiplier has also been designed using this RCPFA and results verified with Xilinx Tool. Proposed circuit design simulations have been carried out in 45-nm process technology using Cadence Virtuoso. The results indicate 57% and 44% reduction in Power and Delay respectively.