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DC Field | Value | Language |
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dc.contributor.author | KUMAR, AJAY | - |
dc.date.accessioned | 2019-10-24T04:45:30Z | - |
dc.date.available | 2019-10-24T04:45:30Z | - |
dc.date.issued | 2019-03 | - |
dc.identifier.uri | http://dspace.dtu.ac.in:8080/jspui/handle/repository/16681 | - |
dc.description.abstract | In this era of internet of things (IoT), the scaling of CMOS is playing a vital role. However, scaling of MOSFETs beyond sub-nm regime is extremely challenging for non-planar device architecture owing to rigorous criteria required for the transistor switching. The stringent scaling may lead to static power dissipation due to increase in OFF-state leakage current. Many solutions have been proposed to overcome CMOS scaling bottleneck with different device architectures such as FinFETs, gate all around silicon nanowire (GAA SiNW), recessed channel (RC) MOSFETs and many more. Although many device structures such as GAA SiNW MOSFETs results in suppression of SCEs, it is not easy to fabricate this due to its non-planar architecture. RC MSOFET offers best possible gate control leading to SCEs and fabrication feasibility for IC industries at very low fabrication cost owing to planar architecture. Different gate materials have been used to improve the gate controllability over the channel and among all; indium tin oxide (ITO) is found to be the most suitable gate material. ITO is very feasible for fabrication and has a very low cost. ITO has a very low resistivity (10-5 Ω-cm) with higher Hall mobility (53.5 cm2 V-1s-1). Due to these properties, ITO is frequently used in semiconductor devices and more commonly, for silicon-based MOSFET devices having technology less than 30 nm. In this thesis, Transparent Gate Recessed Channel (TGRC) MOSFET have been critically scrutinized and compared with the conventional structures using device simulations obtained using ATLAS 3D device simulator. The analysis exemplified that TGRC-MOSFET has overcome the drawbacks faced by the conventional structures and improves the device analog and RF performance owing to trench gate vi Ajay Kumar and ITO metal gate. The improved analog performance and architecture of the device makes it suitable for x-ray dosimeter and bio-sensing applications. In the beginning, the analog and linearity performance of TGRC-MOSFET has been discussed along with the impact of trench depth [Negative Junction Depth (NJD)] and gate length (LG) with an aim to achieve a reliable and high performance transistor. Proposed device improves the analog performance in terms of transconductance, device efficiency, output resistance, and gain. The improved analog and linearity performance at 5 nm NJD and 20 nm LG of TGRC-MOSFET makes it suitable for low power linear RF amplifiers as a nano-scaled device. Further, the reliability issues of the proposed device have been explored by considering the effect of interface trap charges (both polarity and density) in terms of static, linearity and intermodulation distortion FOMs. It is found that with the amalgamation of ITO on conventional recessed channel (CRC) MOSFET, the proposed device exhibits improved immunity against interface trap charges. In addition, the influence of ambient temperature (150-300K) along with trap charges on TGRC MOSFET has also been explored with an aim to analyse at which temperature the device is more stable in the presence of interface defects (trap charges). Moreover, capacitance-voltage (C-V) analysis and frequency dependent capacitance have been analysed with an aim to examine the effectiveness of In2O5Sn as a gate material on parasitic capacitance. The capacitance dependent parameters such as Transconductance Frequency Product (TFP), Energy Delay Product (EDP) and Gain Bandwidth Product (GBP) have also been assessed and found that, TFP increases in comparison to metal gate RC MOSFET owing to a noticeable reduction in parasitic capacitance (Cgg=Cgs+Cgd), due to which EDP and GBP also improve considerably. In order to provide detailed insight to RF engineers for microwave applications, the small signal RF model has been studied in terms of microwave parameters such as S (scattering) parameters, Z (impedance) parameters, Y (admittance) parameters, and h (hybrid) parameters with an aim to analyse the behaviour of device at microwave frequency. It has also been observed that the Ajay Kumar vii transit (cut-off) frequency (fT) and maximum oscillator frequency (fMAX) enhances significantly owing to the remarkable reduction in intrinsic capacitances. After analysing the enhanced electrical properties of the proposed device, it has been explored for an X-Ray dosimeter as well as a biosensor. In the first application, TGRC-MOSFET has used as an x-ray dosimeter where x-ray radiation in the 0.5k to 10kRad dose range after irradiation has been considered. TCAD simulations for the same have been done to estimate threshold voltage shift in MOSFET with different radiation dosage. Models accounting for electron-hole pair generation and recombination are applied along with trap/de-trap model for insulator as well as interface charging. An improvement in radiation sensitivity has been found on increasing the oxide thickness from 2 nm to 6 nm. Along with signal amplification and processing circuit, this device can find enormous applicability in clinical and space environment. Further, the device applications have been extended and used for bio-sensing application. TGRC-MOSFET comprises a nano-gap cavity for the detection of biomolecules and transparent gate to enhance the overall current efficiency of RC-MOSFET. For the detection of neutral biomolecules, following electrical characteristics were studied: ION/IOFF, shift in threshold voltage, change in surface potential and hereafter, calculate the sensitivity of the biosensor. In addition, TGRC noise immunity has been evaluated in the presence of biomolecules. Thus, the high current switching ratio, lower IOFF, lower SS, superior RF performance, temperature robustness, and better reliability in terms of ITCs makes TGRC-MOSFET, a promising candidate for employing in a low power, high switching speed and high performance applications even at wide temperature range. | en_US |
dc.language.iso | en | en_US |
dc.relation.ispartofseries | TD-4495; | - |
dc.subject | TCAD SIMULATION | en_US |
dc.subject | MOSFET | en_US |
dc.subject | TRANSPARENT GATE RECESSED CHANNEL | en_US |
dc.subject | ITO | en_US |
dc.title | ANALYTICAL MODELING AND TCAD SIMULATION OF IN2O5SN TRANSPARENT GATE ELECTRODE RECESSED CHANNEL MOSFET FOR HIGH PERFORMANCE APPLICATIONS | en_US |
dc.type | Thesis | en_US |
Appears in Collections: | Ph.D. Electrical Engineering |
Files in This Item:
File | Description | Size | Format | |
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Revised Thesis_Ajay Kumar_2K16_PHD_EE_05.pdf | 41.8 MB | Adobe PDF | View/Open |
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