IMPLEMENTATION OF ARITHMETIC LOGIC FUNCTIONS FOR LOW POWER VLSI CIRCUITS

Abstract

For the integrated circuit implementation and design, one of the most common design methodology for the implementation of combinational logic circuits is dynamic logic, especially for those logic functions that are implemented using MOS technology. Dynamic logic has certain advantages when compared to the static equivalents in terms of faster speed and requirement of lower surface area. But the area where dynamic logic lacks is that it is more difficult to design and suffers from higher power dissipation.

In order to overcome the issues faced by dynamic logic, Domino logic circuit methods comes into play. Domino logic circuit methodology finds comprehensive use for high-performance design of advanced microprocessors because domino logic topology provides increased speed and improved area usage which is advancement over static complementary MOS(CMOS) circuits. The principal reason of domino logics capability to provide enhances and improved speed is the reduced noise margins in comparison to static logic gates. Domino logic circuits offers some crucial advantages such as improved and higher speed of operation and area saving over the conventional static CMOS logic circuits. These features make domino circuits capable of improved implementation of complex logic gates having larger fan-outs.

The power and delay characteristics of domino logic buffer, pseudo dynamic buffer and footed quasi resistance buffer is verified by VIRTUOSO, CADENCE simulation using 180nm technology.