SETUP & HOLD FIXING OF DIGITAL CIRCUITS WITH AUTOMATED HOLD FIXING USING MULTI SCENARIO ANALYSIS

Abstract

SoC (System on Chip) signoff is considered as a critical part of the SoC design flow. From signoff perspective, an SoC has to pass through multiple criteria before releasing the final GDSII to the foundries for manufacturing Chips, such as Timing criteria, Phyical Verification (PV) criteria, Power Drawn Network (PDN) criteria, Formal Verification (FV) criteria and Conformal Low Power (CLP) criteria. These signoff checks along with many others are performed on an SoC. Timing checks are critical because if we intend to deliver an SoC operating at a desired frequency and speed, it’s important that the chip meets its timing requirements along all the paths. With continuously decreasing technology node, and increasing logic complexity within the chip, the number of scenarios required for timing analysis has also increased. An important stage in performing Static Timing Analysis of a chip is the Engineering Change Order (ECO), where the timing violations are fixed incrementally by giving feedbacks. Usually different paths fail under different conditions or scenarios, hence generating ECO’s for each specific corner and analysing each corner is not recommended as it is time consuming and increases the cost of the chip. Hence Distributed Multi-Scenario Analysis (DMSA) is a feature provided by synopsys PrimeTime tool, which helps the user to simultaneously analyse violations across multiple corners and hence generate ECO’s in a faster and more efficient way. There are two kinds of timing violations that usually happens in a chip namely, setup violations and hold violations. Setup violations are frequency dependent, so they can be resolved by changing the operating frequency of the chip, but hold violations are frequency independent. Hence fixing hold violations require more number of ECO’s to be generated. In my report, I have discussed about an algorithm that efficiently generates Hold ECO’s using PrimeTime tool using Distributed Multi-Scenario Analysis so that each and every violation that occurs across the chip across different scenarios can be captured and fixed.