STATIC POWER REDUCTION TECHNIQUES IN DEEP SUBMICRON TECHNOLOGIES FOR VLSI APPLICATIONS

Abstract

As technology scales down, the size of transistors has been shrinking. The number of transistors on chip has thus increased to improve the performance of circuits. The supply voltage being one of the critical parameters has also been reduced accordingly in order to maintain the characteristics of an MOS device. Therefore, in order to maintain the transistor switching speed, the threshold voltage is also scaled down at the same rate as the supply voltage. As a result, leakage current increases dramatically with each technology generation and reducing leakage power is a great challenge. Static(Leakage) power is a serious problem particularly for CMOS circuits in nanoscale technology. So there is need of proper designing of nanoscale CMOS circuits which reduces the static power without affecting the performance and currently this has become a greater challenge for VLSI designers. In this work we address the sources of power dissipation especially the static power in CMOS circuits and its reduction techniques which reduces the static power to a greater extent. These techniques are utilized to lessen the static power dissipation in many popular combinational and sequential circuits which are the key components of digital IC design. CMOS Inverter, flip flop(DDFF) and ultra-low voltage DTMOS based buffer/Inverter circuits are modified using various leakage reduction techniques like forced Stack, Sleepy stack and LECTOR. These circuits are implemented using Symica DE tool at 45nm & 130nm PTM parameters and the result is compared with conventional circuits, which finally concluded that by using these techniques static power can be decreased to a noteworthy degree which helps circuit designers to handle the static power problem especially for chips that are used in power constrained portable systems.