6T SRAM HIGH DENSITY BIT-CELL ANALYSIS FOR 1PPM FAILURE RATE TARGETTING TEMPERATURE (-40,165)

Abstract

Embedded memories occupies up to 70% of systems on a chip area. In SOC’s applications embedded SRAM’s are often used in order to achieve higher robustness. The main purpose or functionality is to ensure that content of the bitcell are not altered during read operation and bit-cell data could be quickly modified during the write operation. To provide stable read & stable write operation in the SRAM cell, specific conditions are needed to be satisfied. In order to achieve higher robustness there is a need of innovation in the area of SRAM design by scaling SRAM along with CMOS technology. This would help in reducing the variability & increasing the stability while designing the larger SRAM cell. The stability of SRAM bitcell depends on the Static Noise Margin (SNM), Write Margin (WM), and Write time (WT), Dynamic Noise Margin (DNM), ION, ILEAK etc. In this paper we analyzed SRAM read margin, SRAM write margin on the basis of Static Noise Margin Analysis, Dynamic Noise Margin Analysis & Write Margin Analysis. We present the measured result of modified 6T SRAM cell on 28nm bulk CMOS technology. We calculate the safe design space for SRAM overall allowed voltages, temperature & processes. The need of Innovation in the area of SRAM design has been given by scaling the SRAM (Static Random Access Memory) along with CMOS technology in different processors and system-on-chip products rapidly. This would help us in reducing the variability and increasing the stability while designing the larger SRAM cell. However, it is nearly impossible to guarantee the first silicon success in this advanced technology era. In fact more in high density devices like SRAMs, device variations are common. This is because of continuous scaling down of length, width & threshold voltages of the transistor devices. In order to increase the stability of the memory cell and achieve a robust read or write operation, multiple assist schemes and design strategies are used. But variations occurring in the devices are iv

random in nature which degrades the device performance also make it very tedious job to achieve silicon success. This report presents the complete analysis of the high density bitcell by simulating it using ELDO (Mentor Graphics tool) for all device parameters via sizing of transistors and setting the initial conditions. In this work, we conducted a.comprehensive analysis for detecting the memory cells which exhibits weak Static Noise Margin (SNM), write margin and write time identified by the factors causing these cells to exhibit weak properties. For verification of these methodologies in SRAM, a single port high density STM bitcell was considered in 28nm technology.