SIMULATION AND ANALYSIS OF FLASH ADC USING DIFFERENT DYNAMIC COMPARATORS

Abstract

Designing ADC is a new challenge these days owing to the rapid growth of digital technology. Digital signals impart several inherent advantages and are most preferred these days than their analog counterpart. The conversion of analog signal to digital signal is done by ADC. Flash ADC is fastest of all other ADCs and is used for high speed purposes. Comparator is the main building block of ADC. Dynamic comparators provide high speed, low power dissipation and are more area efficient as compared to pre-amplifier comparators. In this thesis, comparison of flash ADC using different dynamic comparators with and without adiabatic logic is done. The circuits are simulated using SymicaDE and LTspice software at 90nm PTM model. It has been concluded that power dissipation can be reduced to great extent by using adiabatic logic without much affecting the propagating delay.