STATIC TIMING ANALYSIS OF A DEEP-SUBMICRON DESIGN

Abstract

Timing holds a very important part in any VLSI design and incorporates the sense of realism into the design. Static Timing Analysis (also referred as STA) is one of the many techniques available to verify the timing of a digital design. Static timing analysis is a complete and exhaustive verification of all timing checks of a design, without requiring simulation. The more important aspect of static timing analysis is that the entire design is analyzed once and the required timing checks are performed for all possible paths and scenarios of the design. Further , the design can be analyzed in various corners to ensure the proper functioning of the design in all the scenarios. Thus, STA is a complete and exhaustive method for verifying the timing of a design. The project is aimed at understanding as well as performing clocking and timing closure of the whole SoC chip. This elaborates on the basic flow adopted to check the timing of a chip, procedures to meet them and debug the errors. The tool used here is ETS which helps in forming detailed reports for finding the violations and simulating the timing behaviour of the circuit.