SIMULATION AND ANALYSIS OF GATE ALL AROUND TUNNEL FET FOR HIGH PERFORMANCE ANALOG AND RF APPLICATIONS

Abstract

Steeper subthreshold swing (SS) and lower OFF-state current (IOFF) accessible by Tunnel FET offers great potentials in low power electronics applications. In this thesis, gate all around Tunnel FET’s performance has been studied and various efforts have been done to overcome the major roadblock of TFET such as the lower ON-state current (ION), ambipolar conduction, higher threshold voltage (Vth) and the higher miller capacitance. In this regard, firstly hetero gate dielectric (HD) and gate metal engineering (GME) are integrated simultaneously on a gate all around TFET i.e. HD-GME-GAA-TFET has been proposed. An analytical model for the proposed HD-GME-GAA-TFET has also been developed for its in-depth inspection. First and foremost, a drain current model for the proposed device is developed, and for the authentication of the developed model, the analytical results so obtained are matched with simulation results. For developing a drain current model, Poisson’s equation is solved by using appropriate boundary conditions and continuity equations to obtain a surface potential profile, lateral electric field and finally by using the generation rate and tunneling barrier width, the drain current is obtained. Developed analytical model and the extensive simulations are used to determine the optimum value of hetero gate dielectrics and dual material gate work functions for acquiring best characteristics of the device. It is analyzed that the ION of GAA-TFET is enhanced from an order of 10-8A to 10-4A with the amalgamation of HD and GME. Furthermore, the SS of 49mV/decade at a Vth of 0.5V has been acquired. Moreover, the influence of gate and drain bias has also been analyzed on the electrical and analog performance of the proposed device. Further, the impact of gate oxide thickness has also been enlightened. It is analyzed that the SS of the proposed device in each case throughout the study, is much lesser compared to 60mV/decade

JAYA MADAN v (fundamental limit on the SS of a conventional MOSFET), proving that the proposed device can be used for high performance switching applications in the future. After analyzing the analog characteristics of HD-GME-GAA-TFET, and to account for the response time, switching speed and active power dissipation; the bias dependent intrinsic parasitic capacitances have been analyzed. The bias dependent parasitic capacitances have been examined under various gate bias, drain bias and also for different metal work function configuration of GME design. Further, for comprehensive RF analysis of GAA-TFET and its effectiveness at high frequency, various RF Figure of Merits (FOMs) such as maximum available power gain, maximum transducer power gain, cut-off frequency (fT), maximum oscillation frequency (fMAX) and intrinsic delay has also been studied for different gate metal work functions of GME engineering scheme integrated on GAA-TFET. The analyzed data would be beneficially providing detailed knowledge about the RF parameters of HD-GME-GAA-TFET at such aggressively scaled dimensions. With the miniaturization of CMOS devices that marks in considerably high integration, the fabrication process damage, stress-induced damage and radiation damage at sub-nm regime result in solemn device reliability issues. These damages originate various interface trap charges (ITCs) at the Si-SiO2 interface and thereby alters the ideal predicted device characteristics and is thus a serious issue that must be scrutinized before circuit designing. Thus, to account for the reliability of HD-GAA-TFET, the device is analyzed under the presence of ITCs of various polarity and density and the results are simultaneously compared with the ideal case in which the interface is free from defects. A comparative analysis of GAA-TFET and HD-GAA-TFET has been done in terms of various analog, RF and linearity parameters to inspect the impact of ITCs and thus the reliability. Results show that the integration of high-k dielectric near source side (to upgrade the device characteristics) concurrently leads to better immunity against the ITCs. Further, to find the pertinence of HDGAA-TFET in wide temperature range ambience, the temperature robustness is also analyzed. Again the device analog and RF characteristics have been investigated at wide temperature range and it is realized that the HD-GAA-TFET and GAA-TFET have bias dependent temperature. Moreover, a severe degradation in IOFF has been obtained at elevated temperatures, whereas at low temperatures (as compared to room temperature), the IOFF reduces appreciably. Thus, the immunity against the ITCs and the marginally increased drain

JAYA MADAN vi current (in ON-state) marks the HD-GAA-TFET an efficient candidate for low power switching applications. Afterwards, for comprehensively upgrading the performance of HD-GAA-TFET, the gate metal is overlapped near drain side that suppresses the ambipolar conduction. Extensive device simulations have been done to examine an optimum gate-drain overlap length (Lov) at which the ambipolar current (IAMB) is reduced efficiently. It is obtained that by overlapping the gate metal over the drain, the IAMB is reduced to an order of 10-17A. Additionally, the applicability of the HD-GAA-TFET as a Hydrogen gas sensor has been suggested by utilizing a Palladium (Pd) metal gate. Primarily, the Pd supported SiO2 is used as a sensing media and sensing relies on the interaction of hydrogen gas molecules with Pd-SiO2-Si. The sensitivity of the proposed gas sensor is compared with its conventional counterparts and it is obtained that the proposed design of gas sensor has appreciably high sensitivity. Further, the stability of the sensor with respect to temperature affectability has also been studied, and it is found that the device is reasonably stable and highly sensitive over the bearable temperature range. The successful utilization of HD-GAA-TFET in gas sensors may open a new door for the development of novel nanostructure gas sensing devices with a sensitivity of the order of 103 i.e. considerably higher than as obtained for a conventional MOSFET. Another effort to overcome the major shortcoming of conventional TFET is done by integrating the efficient engineering schemes i.e. a n+ source pocket and gate-drain underlapping (GDU) on GAA-TFET that form GDU-PNIN-GAA-TFET. The n+ source pocket improves the analog and RF characteristics; on the other hand, the GDU controls the ambipolar conduction. Thereby, the GDU-PNIN-GAA-TFET gathers the collective merits of GDU (reduces the IAMB) and n+ source pocket (enhances ION). Hence, GDU-PNIN-GAATFET results in an up-gradation in the overall performance and offers a SS of 17mV/decade at a Vth of 0.4V, IAMB of 10-18A, and ION/IOFF ratio of the order of 1012. Furthermore, the reliability issues of the PNIN-GAA-TFET have also been discussed. To study the reliability issues, at first, the effect of ITCs polarity, which is common during the pre and post-fabrication process, has been studied on the device analog/RF characteristics followed by the influence of ITCs density. Additionally, to examine the temperature robustness of the PNIN-GAA-TFET various electrical, analog and high-frequency parameters have been examined under different trap charge density and polarity at wide temperature

JAYA MADAN vii range. It is revealed that the donor traps are much hazardous in comparison to acceptor traps. In fact, at substantially higher density of donor traps, the subthreshold characteristics are found to be degraded tremendously that reduces the current switching ratio from an order of 1012 to 105. The temperature associativity reveals that PNIN-GAA-TFET has positive temperature coefficient in contrast to MOSFET. Moreover, the PNIN-GAA-TFET promises bearable immunity against ITCs along with stability to employ under wide temperature range. Thus, the lower SS, high current switching ratio, lower IOFF, superior RF performance, temperature robustness, and better reliability in terms of ITCs makes HD-GAA-TFET and PNIN-GAA-TFET, a promising candidate for employing in a low power, high switching speed and high performance applications even at wide temperature range.