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Title: | DESIGN AND IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK USING VEDIC MATHEMATICS |
Authors: | ANSHIKA |
Keywords: | ARTIFICIAL NEURAL NETWORK VEDIC MATHEMATICS GPS SYSTEMS VLSI TECHNOLOGY |
Issue Date: | Jun-2015 |
Series/Report no.: | TD-2124; |
Abstract: | Artificial neural networks (ANN) play a major role in applications involving DSP. A few to mention include image processing, pattern recognition, GPS systems, speech, vision, and control systems [1-4]. ANN is similar to the human brain and can solve problems which are difficult for the conventional computers, as they can be trained just like the human brain which is not possible for the conventional computers. Additionally, they have attractive properties like adaptiveness, self-organization, nonlinear network processing and parallel processing. This has lead to the use of neural network in applications involving classification, association, decision-making and reasoning [5]. Artificial neural networks consist of massively parallel network and require parallel architecture for high speed operations in real time applications [6]. Also, Neurocomputers and neuro-computing has always been a fascinated topic of research from early 80s and 90s. A lot of research has been done on design and implementation of neural networks and hardware neuro computers [7, 8, 9, 10]. But that time almost all the researches proved unsuccessful in proving the wide use of neural network. But after a long period, literature shows that the concept of neural network and various applications associated with it made a sort of comeback [11, 12, 13]. The main hurdle that was found was ASIC implementation and hence in the last few years, a great revolution has been witnessed in this field due to the use of FPGA which are considered as the best choice for modern digital system designing. Hence, while considering these features neural networks are considered to be best suited for the VLSI technology. The possibility of hardware realization of neural network mainly depends on how efficiently single neuron can be implemented. |
URI: | http://dspace.dtu.ac.in:8080/jspui/handle/repository/16111 |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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Thesis_Anshika.pdf | 1.19 MB | Adobe PDF | View/Open |
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