SIMULATION AND ANALYSIS OF VARIOUS APPLICATIONS OF STATIC POWER DISSIAPTION TECHNIQUE

Abstract

The speed of operation has increased to a greater extent by properly scaling of the CMOS technology, still the issue of leakage currents are leftover as a contrary issue. The issue has taken a severe shift as the scaling enhances into ultra-deep-submicron (UDSM) region. And as the process technology turns into the better state with increment in the device density, it also contributed a lot in increasing the leakage power. As the value of supply voltage decreases, gate oxide thickness reduces which further decrease the value of threshold voltage which contributed in preserving the performance of the circuit. But the main drawback of decreasing the threshold voltage is that the value of leakage power dissipation increases significantly. These unwanted leakage current must be lowered down for proper working of the circuit. So, the proper designing of those nano- CMOS Circuits which provides leakage current free performance advantage and this is the most difficult designing strategy in present era. In this work, we address the issue of leakage power and presents a circuit technique to mitigate the leakage power which in turns reduces the static power dissipation to a greater extent. In the proposed circuits, the static power dissipation is reduced to a greatest extent In popular circuits like SRAM, flip flops by using various techniques like forced stack technique, sleepy stack technique, sleep transistor technique and LECTOR technique. The circuits are implemented using the SymicaDE and LTspice software at PTM models 45nm, and 90nm and the result is compared with the existing techniques, which finally concluded that by using these techniques the leakage power can be decreased to a noteworthy degree.