IMPEMENTATION AND ANALYSIS OF ADDER CIRCUITS USING MODIFIED GLITCH FREE CASCADABLE ADIABATIC LOGIC

Abstract

Nowadays, power dissipation is among the most dominant concerns in designing VLSI circuits. Endless improvement in technology has points to an increased requirement for devices which have the basic characteristic of low power consumption. Hence, power has turned into a demanding design parameter in low power and high-performance applications. The Adiabatic logic technique is becoming a solution to the dilemma of power dissipation. The expression ‘Adiabatic’ indicates to the change of state that takes place without any loss or gain of heat. The power dissipation at the time of switching events can be reduced to a greater extent by using the adiabatic switching technique. Adiabatic logic is a promising design paradigm for low power circuits since the energy which is to be dissipated is recycled and reused back. In most of the digital circuits, digital signal processing and communication systems, multipliers play a major role where adders constitute the basic blocks. Adders with huge power consumption affect the overall efficiency of the system. The research in this thesis unfolds the rising gravity of the issue of the power dissipation and explores different ways to curtail the problem. This thesis includes in depth study of causes of power dissipation, ways of removing a power dissipation in the circuit by using modified GFCAL circuits, along with the proposed application of modified GFCAL technique in various adder circuits. Then, the comparison is made between the conventional CMOS circuit and the modified GFCAL circuit. The functionality and effectiveness of all proposed architectures are confirmed through intensive simulations on SYMICA Development Environment at 90nm technology parameters. All the above introduced circuits are simulated with supply voltage = 0.9 V, 1.2 V and 1.8 V to analyse the pattern followed with supply variation. Similarly, the calculation of delay is performed for temperature values of 27˚C, 55˚C and 120˚C at 90nm technology. Effect of proposed applications on the delay of the circuit has been analysed as well.