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Title: | VERILOG IMPLEMENTATION OF DIGITAL IMAGE WATERMARKING |
Authors: | SATYAN |
Keywords: | VERILOG IMPLEMENTATION DIGITAL WATERMARKING DIGITAL IMAGES FPGA |
Issue Date: | Jul-2017 |
Series/Report no.: | TD-3006; |
Abstract: | The development of computer technology has brought about growth in the use of digital multimedia contents related to electronic commerce and services provided through internet. As digital media is easily regenerated and manipulated, so everyone is potentially at risk or incurring considerable financial loss. Also people are motivated to embed data or information such as owner information, company logo, date, time, brand name and even hide a secret message in the digital images to communicate secretly. Digital watermarking can prevent such a loss by providing authentication and copyright protection and plays an important role in security of important data or the content of digital media. The digital images are easily exchanged through internet and threaten to various malicious attacks so they must be protected based on copyright. Here the project represent an efficient hardware implementation of digital Watermarking which features low power consumption, simple implementation, increased processing speed, reliability and invisible image watermarking. Proposed concept would be implemented using Verilog and synthesize Into FPGA. |
URI: | http://dspace.dtu.ac.in:8080/jspui/handle/repository/16024 |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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Thesis.pdf | 1.64 MB | Adobe PDF | View/Open |
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