LEAKAGE POWER REDUCTION IN DYNAMIC DCVSL USING ONOFIC APPROACH

Abstract

Differential logic styles have been becoming popular over conventional CMOS logic because of they promise lower power consumption and high computational speed. DCVSL promises the advantages of both traditional CMOS logic and pseudo NMOS logic thus offering high speed area effective rail to rail swing logic option. The dynamic DCVSL logic family has been explored and leakage power and delay has been considered. Various dynamic versions of DCVSL logic have been introduced and their leakage power and delay have been studied. Leakage power is an important issue in dynamic circuits and a leakage control technique (LECTOR) has been explored in context of two variations of dynamic DCVSL structures. The LECTOR technique is applied to other variants of dynamic DCVSL structures and performance in terms of leakage power dissipation, propagation delay time, power delay product, transistor number is examined. In this thesis, a relatively new leakage reduction technique known as ONOFIC technique has been successfully proposed in various DCVSL structures. Various performance related parameters and transistor count has been reported. This thesis includes relative performance comparison of dynamic DCVSL structures in their conventional format and with the introduction of LECTOR and ONOFIC approach. The effectiveness and functionality of all dynamic DCVSL structures and proposed architectures are confirmed through intensive simulations on Symica Design Environment. The structures were implemented using Symica Design Environment (Symica DE) using 90 nm PTM model technology at 1.2V to analyse the variation in leakage power and delay.