STUDY OF LOW-POWER PULSE-TRIGGERED FLIP-FLOPS

Abstract

Flip-flops and latches are important elements of a digital system design in terms of both a delay and energy stand point. The choice of flip-flop implementation is of essential importance in design of VLSI integrated circuits for high speed, low power and high performance CMOS circuits. In this work, low-power pulse triggered flip-flop (P-FF) designs namely Explicit Type Data-close-to-output (ep-DCO), Conditional Discharge Flip-flop (CDFF), static CDFF and a true single phase clock latch based on a signal feed-through scheme (SFTFF) are studied. Former three fall under conventional P-FF and have limitation of long discharging path issue whereas SFTFF design successfully resolves this and achieves better speed and power performance. The timing parameters for Simulation results are obtained using PTM BSIM4 CMOS 90-nm technology, SFTFF design performs better than the conventional P-FF designs in view of data-to-Q delay.