TCAD ANALYSIS AND SIMULATION OF GATE ELECTRODE WORKFUNCTION ENGINEERED (GEWE) SILICON NANOWIRE MOSFET FOR HIGH PERFORMANCE ANALOG AND RF APPLICATIONS

Abstract

Scaling MOSFETs beyond sub-nm gate lengths is extremely challenging using planar device architecture due to the stringent criteria required for the transistor switching. The development of three dimensional devices like Multi-gate MOSFETs, ultra-thin SOI MOSFETs, FinFETs, Silicon Nanowires, Nanotubes etc. become important for the further advancement in the integrated chip industry. The top-down fabricated, gate-all-around architecture with a Si nanowire channel is a promising candidate among these for future technology generations. The gate-all-around geometry enhances the electrostatic control and hence gate length scalability and also suppress short channel effects effectively. Silicon nanowire MOSFET in gate all around configuration has proved to be good candidate due to its ability to suppress short channel effects. In nanoscale MOSFET, to improve speed and performance of a device, several engineering schemes have been proposed but the main problem associated is gate transport efficiency. As dual gate-MOSFET and Split Gate-MOSFET structures cannot improve both carrier transport efficiency and shortchannel effect. Gate Electrode Workfunction Engineering structure opens a new way to improve device performance. To eliminate polysilicon depletion width effects and polysilicon dopant penetration, polysilicon gates need to be replaced by metal gates. In 1997, Wei vi NEHA GUPTA Long and Ken K. Chin proposed a novel structure the Dual Material Gate MOSFET, which suppress short channel effects and enhance carrier velocity. In the DMG-MOSFET, the gate consists of two contacting materials with different work functions. The metal with higher work function is close to source and metal with lower work function is close to drain, and hence threshold voltage VT1>VT2 which improve the carrier transport efficiency. It is observed the step potential profile in the channel region because of two metal gates of different work function, which ensures reduction in short channel effects without sacrificing other device characteristics, unlike in dual gate or other gate structures. In this dissertation, gate metal workfunction engineering scheme is amalgamated onto SiNW MOSFET and its Hot-Carrier fidelity and DIBL are studied to scrutinize its efficacy in high power CMOS applications. It is found that with k = 21(HfO2) as gate oxide, device performance in terms of hot-carrier reliability further enhanced due to increased capacitance and thus offer its effectiveness in subnm range analog applications. Extensive device simulation results shows that GEWE-SiNW MOSFET exhibit improved RF performance in terms of high cut-off and maximum oscillator frequency and its performance further intensified with tuning of device parameters such as gate length, radius of nanowire, oxide thickness and workfunction of gate metals. Thus, providing detailed knowledge about the device’s RF performance at such aggressively scaled dimensions. For comprehensive RF analysis of GEWE-SiNW MOSFET and its effectiveness at HF, the small signal behaviour in terms of scattering parameters is also discussed. This would be useful for evaluating the microwave performance of the device in terms of forward and reverse gains. In addition, noise metrics have also been evaluated which affects the device performance at HF. The RF investigation carried over is circumscribed to intrinsic components of MOSFET only. However, NEHA GUPTA vii at GHz frequency range, the importance of extrinsic component (the part outside the channel region) dominates to that of its intrinsic counterpart. Therefore, there is a need for an RF model which should consider the behaviour of both the intrinsic and the extrinsic components of a device for achieving accurate and predictive results in the simulation of designed circuit. Thus, the extrinsic and intrinsic parameters of GEWE-SiNW MOSFET and numerical modelling of small signal parameters such as Z and Y parameters are also studied in this work. Furthermore, as oxide thickness scales down to 1.5 nm or below, the leakage current increases up to 1 A/cm2 at 1 V due to direct tunneling of carriers which, consequently increases the static power and hence affect the circuit operation. So, high-k films are proved to be the most promising solution. Though, these films result in high fringing fields from gate to source/drain regions and thus degrading the device performance. This constraint can be overcome by using gate stack architecture consisting of SiO2 layer as a passivation between high-k films and bulk by keeping the effective oxide thickness (EOT) constant, high-k dielectrics permit the increase in physical oxide thickness to prevent gate tunneling and thus improves the carrier efficiency. Thus, stack gate (SG) is amalgamated onto GEWESiNW MOSFET to examine its performance in terms of analog and linearity FOMs. It is observed that SiNW MOSFET modeled with HfO2 as a gate stack over SiO2 interfacial layer, and gate metal workfunction difference (ΔW) of 4.4 eV can be considered as a promising potential for low power switching component in ICs and Linear RF amplifiers. Moreover, a reliability issue of Stacked Gate (SG)-Gate Electrode Workfunction Engineered (GEWE)-Silicon Nanowire (SiNW) MOSFET is examined over a wide range of ambient temperatures (200–600 K). It is observed that at low temperature SGviii NEHA GUPTA GEWE-SiNW shows improved Analog/RF performance in terms of Ion/Ioff, Subthreshold Swing (SS), device efficiency, fT, noise conductance and noise figure and also unveil highly stable linearity performance owing to reduced distortions. The results so obtained can be serving as a worthy design tool for circuits operating at wide range of temperatures. Immunity against SCEs, high current driving capability, optimum high frequency performance and suitability at low temperature makes GEWE-SiNW MOSFET a promising device for low power, high performance CMOS applications.