DADDA MULTIPLIER BASED HARDWARE FOR CONVOLUTION OPERATION

Abstract

Multiplier is a central block in the Digital Signal Processor (DSP). In order to improve speed of processing, a hardware convolution unit is embedded in the design of multiplier. Convolution unit performs multiplication and addition process. Basic Convolution unit consists of multiplier, adder. Generally convolution unit is designed using different Multiplier and adder as Carry Save Adder (CSA). The proposed Convolution unit is designed using Dadda Multiplier (DM) and adder as Logically Optimized Full Adder (LOFA).However in the proposed model all traditional full adders are replaced by improved full adder. The performance analysis of Convolution unit models in terms of area, delay and power are compared. Various Convolution unit models are designed using Verilog HDL. Simulation and synthesis are done using Xilinx ISE 14.7 for Virtex-7 family 40nm technology device. The power is calculated using Lattice Diamond Design suite software.