A NUMERICALLY EFFICIENT IMPROVED CHANNEL LENGTH ANALOG BEHAVIOURAL MODEL OF CNTFET AND APPLICATIONS

Abstract

Ever since the 0.35 μm node, the gate length of MOSFET has entered the deepsubmicron region. 65 nm technologies becomes the mainstream since 2006, and 45 nm technology has been announced in 2007. As CMOS continues to scale deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered MOSFETs. It becomes more difficult to further improve device/circuit performance by reducing the physical gate length. The discrepancy between the fabricated physical gate length and the ITRS projected gate length becomes larger as the technology advances. Recognizing that the device structure has been scaled from 3-D (bulk CMOS), quasi 2-D (partially depleted SOI), 2-D (fully depleted SOI), quasi 1-D (nanowire FET, FINFET, tri-gate FET), to 1-D (CNFET) for better channel electrostatics, it is important and necessary to model the behavior of 1-D device with the aim of guiding 1-D device and circuit design. This thesis describes a body of work on modeling, implementation and understanding for nanoscale devices, carbon nanotube field effect transistors (CNFETs), with the aim of making the device model more numerically efficient and improving the channel length, as well as enhancing the accuracy of channel current by introducing the band to band tunneling current (Ibtbt). This work will also lead to the nanoscale device based circuit design in the field of analog and digital domain applications. Analog behavior modeling carbon nanotube FET has been implemented using HSPICE. Later part of the thesis is implementation of digital logic gates as digital domain application and implementation of precision full wave rectifier using differential difference current conveyor (DDCC) as analog domain application.