REALIZATION OF ADDRESS GENERATOR FOR WIMAX USING FPGA

Abstract

The demand for mobile broadband access for internet and multimedia based applications has given rise to scalable network architecture which can provide such services at a lower cost to the operators and the end users. The IEEE 802.16e standard or the WiMAX (Worldwide Interoperability for Microwave Access) standard provides a solution to the Broadband Wireless Access with an extended feature of mobility support. In the WiMAX transceiver structure a channel coding block is employed in order to prevent the errors during transmission and correct them on the receiver end. The interleaver block in this module performs an important role to reduce the effect of burst errors by spreading the sequential or the adjacent data words through several transmitted bursts. This is done by a sequence of permutation steps, and on the receiver side the reverse operation of these steps is carried out in order to recover the data. The floor function required for these permutations is difficult to implement on FPGA. So a simple mathematical algorithm has been shown in this work eliminating the use of floor function. Also the modulus 3 function has been proposed using a set of binary parallel adders which can be used as an alternative for ROM circuitry. In this work, an address generation circuitry for WiMAX deinterleaver has been designed using Verilog HDL and the results have been simulated on ISim Simulator. The proposed work enhances the operating frequency and gives a low complexity circuit as compared to earlier work in terms of performance parameters for FPGA.