DESIGN AND IMPLEMENTATION OF GOLAY CODES

Abstract

In recent years demand is increasing day by day for digital transmission of data and storage systems. VLSI technology and digital processing techniques are also acting as a supporting factor for this demand. In digital communication it is highly required that it must be fully reliable, as a single error can corrupt the data or can cause complete shutdown of the system, e.g. in online transaction of money. So digital communication systems must be fault tolerant as well as capable of detecting errors and recover it. The easiest way to detect a single error is a parity checksum method which can be implemented with the help of XOR gates. But with the advent of VLSI technology has entered in an era of Nano scale design where number of components on the single chip ranges from 1, 00, 000 to 10, 00, 000. As the number of components increase on the chip, the complexity increases due to large number of interconnections. So, for such cases parity check sum method is not a suitable technique to be used for error detection. Hence, some new coding techniques are required for data transmission. Various types of Error Control coding schemes like BCH codes, Reed- Solomon codes, Turbo codes, Convolutional codes, LDPC codes are implemented now a days. One of these techniques is Golay encoding and decoding scheme which is used as basic motivation for the purpose of this thesis. Also advanced Golay codes are designed so that Golay codes can be made more reliable and sophisticated.