SYSTEMATIC STUDY OF HIGH SPEED ADDERS AND THEIR MCML REALIZATIONS

Abstract

There is shift in trend to current mode circuits due to their inherent advantage of reduced power consumption and high speed performance. Recently MOS Current Mode Logic (MCML) has gained interest and is dealt in this thesis. This topology is suitable for high speed design in mixed signal environment. One of the most important and frequent used structure in numerous processors and digital filters are adders. The overall performance of the block is affected by the delay incurred in addition operation. Hence use of high speed adder structures is in need. This thesis presents study of various adder structures and their implementation using MCML style. When the number of bits in the input words is large, the MCML square root carry select adder is a viable alternative to MCML ripple carry adder and therefore it is designed. Significant improvement in delay was obtained for 16-bit MCML square root adder. When the input word is small, parallel prefix adders are considered to be the fastest one and therefore MCML approach is utilized to design parallel-prefix adders. The computation speed can further be enhanced by using Ling’s scheme, hence MCML Ling adders which can be used as a viable choice for MCML parallel-prefix adders has been designed. All these adders inherit the advantages of MCML circuit over CMOS style as internal part of the adder is constructed using MCML basic gates. The Ling adders are designed with Brent Kung, Kogge Stone, Sklansky, Han Carlson, Ladner Fischer and Knowles tree structures. Their performances have been compared with 16-bit parallel-prefix adders employing the same tree structures. The simulation results prove the high speed nature of MCML Ling Adders. The reduction in delay in MCML ling adders implemented with six different tree structures varied from 35.69% to 4.62% with maximum reduction observed in MCML Han Carlson Ling adder and minimum delay seen in MCML Kogge Stone Ling adder. The workability of all proposed adders is confirmed through PSPICE simulations using TSMC 180 nm CMOS technology parameters.