LEAKAGE POWER REDUCTION IN DUAL DYNAMIC HYBRID FLIP FLOP (DDFF) USING LECTOR INVERTER PAIR

Abstract

The rapid growth in semiconductor technology and increasing demand for portable devices powered up by battery has led the manufacturers to scale down the feature size, thereby enabling integration of extremely complex functionality on a single chip. The threshold voltage is also reduced due to scaling which has resulted in increased sub-threshold leakage current which is referred as static power dissipation. According to ITRS (International technology road-map for semiconductors), leakage power is becoming a dominant part of total power consumption. To prolong the battery life of portable devices, leakage power reduction is the primary goal. One of the objectives of this thesis is to study various leakage components and different leakage power reduction techniques. The second objective is to study various flip flops and apply leakage reduction technique. Dual Dynamic Hybrid Flip Flop (DDFF) is chosen to investigate leakage current as it belongs to hybrid flip flops and has advantages of both dynamic and static design. LECTOR technique is applied to DDFF as does not require extra control input for control signal generation. The DDFF with LECTOR technique is referred as DDFF_LECTOR in this work. To check the authenticity of theory, simulations are carried out using SYMICA Development Environment Tool. All the circuits are simulated at 45nm technology node. Various performance parameters have been examined and it is found that leakage current in DDFF_LECTOR is state dependent. The saving in best case is 51% while its value is 28% in worst case. The effect of power supply reduction and temperature on leakage current is also studied.