INVESTIGATION OF LEAKAGE POWER IN DCVS LOGIC FAMILY

Abstract

Rapid scaling of transistor dimensions in accordance with Moore’s law due to brisk demand of high speed portable electronic device has led to drastic upsurge in leakage currents in the device leading to unnecessary leakage power dissipation. The research in this thesis unfolds the rising gravity of the issue with continuous technology advancement and explores different ways to curtail the problem. Of late, a shift of trend from conventional CMOS logic to differential logic styles has been witnessed due to their in-built features of lower power consumption and high speed. DCVSL which is one of the differential logic families is an efficacious blend of the advantages of traditional CMOS logic and pseudo NMOS logic and offers a high speed, area effective and rail to rail swing logic design option. Henceforth, DCVS logic family has been explored in this thesis to exploit its inherent advantages and moreover its leakage power aspect has been dealt deeply to introduce low power DCVS logic which works well at lower technology nodes. This thesis includes in depth study of causes of leakage power in devices and techniques to regulate leakage current at circuit level for CMOS logic circuits. Trends followed by leakage current with variation in supply and technology are studied and verified. LECTOR technique used for CMOS logic has been adapted and aptly applied to static, dynamic and enhanced DCVS logic which achieves a significant saving in leakage loss for DCVS logic circuits. Various basic logic circuits are implemented using DCVSL style and their low power versions are proposed by adapting studied methodologies which are leakage power efficient. Hybrid configurations involving combination of transmission gate logic and DCVS logic are proposed for two input and three input XOR gates for static, dynamic and enhanced DCVS logic. Hybrid configuration proves to be more efficient in terms of leakage power saving. Furthermore, LECTOR incorporated versions of hybrid configurations are introduced which achieves even more leakage saving when compared to basic DCVSL configuration. The functionality and effectiveness of all proposed architectures are confirmed through intensive simulations on SYMICA Development Environment at 90nm, 65nm and 45nm technology parameters (leakage effect is more predominant below 180nm). All the above introduced circuits are simulated with VDD=1.8V and 1.2V to analyse the pattern followed with supply variation. Similarly, temperature variation is performed for temperature values of -25oC, 27oC and 100oC at 45nm technology and VDD=1.2V. Effect of proposed configurations on the delay of the circuit has been analysed as well.