ADAPTIVELY BIASED CMOS VOLTAGE FOLLOWER

Abstract

A novel CMOS adaptive biasing technique has been proposed for low power applications which can be applied to any CMOS circuit having differential current at one of its node. This technique gives an output current proportional to input differential voltage. The proposed technique can be used in low voltage high speed operational amplifiers. The dynamic bias current saves power and also improve slew rate, delay. A modified NMOS topology technique is also applied to a conventional operational amplifier to improve the slew rate. A SPICE simulation for proposed technique and modified NMOS topology technique in 0.18um CMOS technology is reported.