REALIZATION OF DELAY LOCKED LOOP USING VCDL IN 180NM CMOS TECHNOLOGY

Abstract

A proper operation of synchronous circuits requires tight control on clock signals which necessitated the use of clock synchronization circuits. Delay Locked Loop (DLL) is one among these circuits which has superior stability. The DLL uses a phase frequency detector to detect phase error between input reference clock and the output clock, a combination of charge pump and loop filter to generate control voltage and a Voltage Controlled Delay Line (VCDL) to delay the reference clock so that there is no skew between reference clock and output clock. The PFD block has been realized using NAND gates and inverters and C2MOS based register. Two modifications are also suggested in C2MOS based realization. This work aims at implementing a DLL and studies its performance.