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DC Field | Value | Language |
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dc.contributor.author | SHAIKH, MOHAMMAD RIZWAN UDDIN | - |
dc.date.accessioned | 2016-07-04T04:43:41Z | - |
dc.date.available | 2016-07-04T04:43:41Z | - |
dc.date.issued | 2016-06 | - |
dc.identifier.uri | http://dspace.dtu.ac.in:8080/jspui/handle/repository/14876 | - |
dc.description.abstract | ALU is a central block in the computing devices, especially Digital Signal Processor (DSP). Basic ALU consists of arithmetic unit, logic unit and control unit.In order to achieve high performance MAC unit is incorporated in the design of ALU.MAC unit performsmultiplication and accumulation process. Basic MAC unitconsists of multiplier, adder, and accumulator.In the existing MAC unit designed using Dadda Multiplier and adder as Carry Save Adder (CSA). The proposed MAC unit designed using Dadda Multiplier and adder as Carry Increment Adder (CSA).However in the proposed model all traditional full adders are replaced by improved full adder. The performance analysis of MAC unit models in terms of area, delay and power is done.Various MAC unit models are designed using Verilog HDL. Simulation and synthesis are done using Xilinx ISE 12.2 for Virtex-6 family 40nm technology device. The power is calculated using Lattice Diamond Design suite software. | en_US |
dc.language.iso | en_US | en_US |
dc.relation.ispartofseries | TD NO.1962; | - |
dc.subject | MAC UNIT | en_US |
dc.subject | CARRY SAVE ADDER | en_US |
dc.subject | SIMILATION | en_US |
dc.subject | ALU | en_US |
dc.title | DESIGN & PERFORMANCE ANALYSIS OF MAC UNIT | en_US |
dc.type | Thesis | en_US |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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Thesis.pdf | 4.92 MB | Adobe PDF | View/Open |
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