DESIGN AND IMPLEMENTATION OF EFFICIENT REVERSIBLE MULTIPLIER USING VEDIC MATHEMATICS TOOL

Abstract

Multiplier is one of the important block in almost all the arithmetic logic units. These multipliers are mostly used in the fields of the Digital Signal Processing (DSP), Fast Fourier Transform, convolution, filtering and microprocessor applications. A system's performance is generally determined by the performance of the multiplier, because the multiplier is generally the slowest element in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. Since multiplier is the main component and hence a high speed and area efficient multiplier can be achieve by using Vedic mathematics. In this work we have implemented the Vedic multiplier using Chinese Abacus Adder with and without using Reversible logic gates. Reversible logic is one of the promising fields for future low power design technologies. Since one of the requirements of all DSP processors and other embedded devices is to minimize power dissipation multipliers with high speed and lower dissipations are critical. This work is devoted to the design of a high speed Vedic multiplier using reversible logic gates. For arithmetic multiplication, various Vedic multiplication techniques like Urdhva Tiryakbhyam, Nikhilam and Anurupye have been thoroughly discussed. It has been found that Urdhva Tiryakbhyam Sutra is the most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large. Further, the Verilog HDL coding of Urdhva Tiryakbhyam Sutra for 32x32 bits and 64x64 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 3E kit have been done. The synthesis results show that the computation time for calculating the product of 4x4 multiplication is less as compared with other conventional multipliers.