PERFORMANCE EVALUATION OF CML BASED SERILALIZER/DESERIALIZER

Abstract

ABSTRACT In communication systems, serializers and deserializers are the common and important building blocks. They are used in optical networks for purpose of telecommunication for long distance as well as for high speed connections over small distance comparable to the length of circuit board, to meet higher data bandwidth. Since CMOS based circuits have this huge disadvantage of larger power dissipation at higher frequencies, this has led to a shift in trend to current mode circuits as they have innate advantage of higher speed performance because of reduced voltage swing and much less power consumption at higher frequencies, as compared to CMOS based circuits. This thesis provides novel Serializers and deserializers for which triple-tail MCML cell based Dlatch with feedback resistors has been used as basic building block which is not only immune to various device mismatches caused by threshold voltage fluctuation and also operates at higher frequencies as compared to simple MCML based D-latch and triple-tail based MCML D–latch. MCML D-latch uses two stacked transistors for logic implementation and puts a limit on minimum power supply that can be applied and hence have huge static power dissipation. This static power can be further reduced by decreasing the power supply, for which triple-tail MCML based D-latch, has come into picture, which uses one stack of transistors in PDN and hence can operate at low power supply as compared to traditional MCML D-latch. Despite of being shown that MCML circuits consumes less power as compared to CMOS at operation frequencies of very high in range, designers are showing reluctance to replace CMOS with MCML because its performance is greatly affected by the fluctuation of threshold voltages of the differential pair transistors of PDN network because of its differential nature.