IMPLEMENTATION OF SINGLE CORE L1 L2 CACHE WITH THE COMPARISON OF READ POLICIES USING HDL

Abstract

ABSTRACT This thesis focuses on the comparison of three different replacement policies for Cache memory by using hit rate as the performance criteria. Random, LRU and Pseudo-LRU. It involves the implementation of 2-way, 4-way and 8-way Set Associative mapping technique for varying cache sizes. For the sake of comparison a 4KB ,8KB ,16KB ,32KB, 64KB,cache memory is taken as base on which the policies are executed. The implementation of the memory controller and the required glue logic is carried out. Test bench is written for simulating the input signals to the memory controllers. At the next level, a higher capacity L2 cache memory is considered and the same process is repeated to estimate the performance with respect to Hit Rate. Verilog language is used for the hardware implementation. Memory controllers for the Main Memory, L1 Cache and L2 Cache are realized using Verilog language. As we double the Way of cache (2-Way to 4-Way & 4-Way to 8-Way) the performance increases in general, but the percentage increase is not same. 2-Way to 4-Way increased by~3.5%, 4-Way to 8-Way increased by ~0.2%. It implies that we won’t get equal performance increment on doubling the Way-Size of cache. To find the optimized Way-Size we have to strike a balance between the Cache-Size and Hit-Rate. In our case optimized Way-Size is 4. Performance increment also depends upon the program in execution. So the optimized Way-Size can be different for different program.