IMPLEMENTATION OF HALF ADDER USING RECESSED CHANNEL MOSFET BASED ON MIXED-MODE SIMULATION

Abstract

We observe that in the past few decades the minimum size of transistor has been downscaled according to the Moore's law. But now further downscaling of MOSFET is facing challenges like SCE(short channel effects), gate insulator tunneling. To overcome these challenges Recessed Channel MOSFET, a type of grooved device, is the most promising device structure. RC-MOSFET technology has the caliber to continue with the Moore’s law. RC-MOSFET has started replacing conventional MOSFETs. RC-MOSFET is a non planar structure in which the drain and source regions are separated from one another through a groove, the extension of the drain electric field toward the channel region is restrained. The presence of groove minimizes the SCEs and punch through effects, thereby enhancing the hotcarrier reliability. This thesis work analyses the implementation of Half Adder circuit using RC-MOSFET based on MixedMode simulation and also analyses through literature survey the effects of variation in various device parameters like drain current(Ion), threshold voltage(Vt), DIBL and subthreshold swing(S), impact ionization of RC-MOSFET by using simulation tools 3D Silvaco ATLAS version5.16.3.R and Devedit version 2.6.0.R.