LOW POWER PSEUDO DYNAMIC BUFFER WITH DYNAMIC LOGIC

Abstract

Dynamic logic circuit is the main digital circuits, with a clock as a controlling signal. Comparing with the complementary logic circuit which is having both Pull-up and Pull-down network, dynamic logic circuit has only one network. Dynamic logic circuits consume nearly half of the transistor count as well as the layout area. Parasitic capacitances are used to stored the voltage at the output of the dynamic node, which is typically buffered before it is sent to the next stage. This voltage is affected by the charge sharing. Advantage of dynamic logic circuit is having smaller area and higher speed. According to the theory, the dynamic logic circuit will uses precharge and evaluation phases of the clock cycle. During the precharge phase, a lot of extra noise are introduced into the system compared with the static logic circuit. A noticeable amount of power is waisted due to these periodic precharge phases. Here we propose a Low power pseudo dynamic buffer structure for the dynamic logic circuit. Using this dynamic buffer structure, the precharge pulse is obstructed at the input of the dynamic buffer and is supress from being propagated to the output of the dynamic gate. As a result, power typically consumed during the precharge phase is saved. According to the proposed structure will dramatically reduce the output noise as well as considerable power consumption compared to the traditional dynamic buffer circuits.